Awards
Awards
ULTRARAM™
Tech Overview
ULTRARAM™ is a remarkable, patented, memory technology developed by Lancaster University. It exploits a quantum-mechanical process called resonant tunnelling, allowing ULTRARAM™ to deliver non-volatility with fast and energy-efficient write and erase, resulting in high endurance. This combination of properties was thought to be unachievable until now. ULTRARAM™ has the non-volatility of flash, with a performance that is expected to exceed that of DRAM.
The $165bn pa memory market is dominated by dynamic random-access memory (DRAM, $100bn) and NAND flash ($60bn). Flash is non-volatile, retaining data when unpowered, but is slow and has poor program/erase cycling endurance. In contrast, DRAM is fast with excellent endurance, but it is volatile, and requires data to be constantly refreshed. For decades there has been a quest for a memory that combines their advantages without their disadvantages, i.e. a memory that is fast and non-volatile, with high endurance and ultra-low switching energies; a so-called ‘universal memory’. ULTRARAM™ has achieved these universal memory characteristics.
Quantum Technology
ULTRARAM™
ULTRARAM™ is a flash-like floating-gate memory. However, unlike flash, which uses a highly-resistive oxide barrier to retain charge in the floating gate, ULTRARAM™ uses atomically-thin layers of InAs/AlSb to create a triple-barrier resonant-tunnelling (TBRT) charge-confining structure. The TBRT switches between a highly-resistive (locked) state (with no bias, ‘store’), to a highly-conductive (unlocked) state on application of just 2.5 V across the gate stack (program/erase). It is this mechanism that gives ULTRARAM™ its remarkable properties.
Quantum Technology
ULTRARAM™
ULTRARAM™
Unlike DRAM and flash, which are silicon based, ULTRARAM™ uses III-V compound semiconductors. Specifically, the so-called 6.1-angstrom family of semiconductors (GaSb, InAs and AlSb). This allows engineering of the memories’ electrical properties to exploit the underlying physics to full effect, whilst also being capable of volume manufacture using established processes in the compound semiconductor and silicon industries. The extremely low electron-effective-mass in InAs also opens the possibility for a new high-speed embedded III-V logic to address arrays.
Energy Efficiency
The factors determining energy efficiency vary widely for different memory technologies. For example, many emerging memories function by making/breaking interatomic bonds or by switching atomic magnetic moments. These processes are energy intensive, resulting in high program/erase energies. Charge based memories such as flash and DRAM are superior in this respect as they manipulate electrons rather than atoms, which requires less energy. However, there is still room for even greater efficiency!
With its combination of low capacitance and low voltage program/erase, ULTRARAM™ has a switching energy per unit area that is 100x lower than DRAM, 1,000x lower than flash and over 10,000x lower than other emerging memories. ULTRARAM™’s ultra-low energy credentials are further enhanced by its non-destructive read and non-volatility, which removes the need for refresh.
Program Erase / Switching Energies
10,000 x
Lower than other emerging memories
100 x
Lower than DRAM
Program Erase / Switching Energies
1,000 x
Lower than Flash
ULTRARAM™
High Endurance
Endurance refers to the number of times a memory cell can be programmed/erased before it is worn-out. This is a weakness of non-volatile memories such as flash, which typically only withstand 10,000 program/erase cycles. In contrast, ULTRARAM™ has demonstrated degradation free operation in excess of 10 million program/erase cycles. This is due to the low-voltage, ultra-low-energy program/erase process enabled by quantum resonant tunnelling.
Non-Volatility vs Speed
A memory is non-volatile if it is able to retain data when unpowered, requiring a robust logic state that is difficult to change, e.g. flash. In contrast, a fast memory seemingly requires the logic state to be frail so that it can be changed quickly and easily, e.g. DRAM. Therefore, a memory that is fast and non-volatile seemingly requires contradictory physical properties and has long been dismissed as unachievable.
ULTRARAM™ breaks this paradigm through the use of quantum mechanics and resonant tunnelling. Extrapolated retention times in excess of 1,000 years have been demonstrated and scaling of devices down to state-of-the-art feature sizes is predicted to achieve speeds that match or exceed DRAM.
Our Team
QuInAs Team
CEO
James Ashforth-Pook
James Ashforth-Pook has over 30 years’ experience in corporate and start-up management. James was Vice President at Unisantis Electronics Tokyo/Singapore, founded by the inventor of flash memory, developing surrounding gate transitiors for future memories in partnership with imec, Samsung and Micron. He was Director/General Manager at Cadence Design System/Quickturn and Director European Strategic Group of Synopsys, Grenoble, where he brokered a multi-$M partnership with ARM. He setup and managed the European group of Applied Microsystems Corporation, Paris, establishing relationships with Intel and Motorola. James holds a Bachelor of Science in Electrical Engineering from University of Plymouth.
CSO
Manus Hayne
Prof Manus Hayne has 35 years’ experience researching semiconductor nanostructures and is the inventor of ULTRARAM. Manus is currently Deputy Head, Director of Research, Director of Business Engagement and Impact Champion at the Department of Physics, Lancaster University. He has previously worked as a researcher at the University of Exeter, CNRS in Paris and at KU Leuven. Manus has collaborated extensively with industry, including projects with AIXTRON, BT, Integrity Scientific, IQE, IP Pragmatics and nextnano. He has co-authored more than 100 scientific papers, with 2000 citations. Manus holds a Bachelor of Science in Physics with Electronics from Southampton University and a PhD in Physics from the University of Exeter.
CTO
Peter Hodgson
Dr Peter Hodgson has 14 years’ experience in the field of III-V compound semiconductor nanostructures and devices. During his time as a Senior Research Associate at Lancaster University, he has published 16 scientific papers and developed technical expertise in device design, molecular beam epitaxy, x-ray characterisation techniques and photoluminescence. Peter has secured over £300k funding for projects related to the technical development and commercialisation of ULTRARAM memories. He has worked on collaborative R&D projects with industry partners, including IQE, BT, Compound Semiconductor Technologies and IP Pragmatics. Peter holds a PhD and a Master’s degree in Physics from Lancaster University.
FINANCE
Mark is a commercial board level Finance Director with considerable experience working in a financial and commercial environment with particular focus on scaling SME’s to a trade sale. He has held a variety of senior financial positions at Samsung, APW Inc, Invensys Plc, NXP and Jennic and lately as CFO for technology startups Surecore, Secure Thingz, Faradion and Additive Manufacturing Technologies. Mark is a member of the Institute of Chartered Accountants in England and Wales and has a Bsc. (Hons) in Finance and Accounting.
Mark Long
Mark is a commercial board level Finance Director with considerable experience working in a financial and commercial environment with particular focus on scaling SME’s to a trade sale. He has held a variety of senior financial positions at Samsung, APW Inc, Invensys Plc, NXP and Jennic and lately as CFO for technology startups Surecore, Secure Thingz, Faradion and Additive Manufacturing Technologies. Mark is a member of the Institute of Chartered Accountants in England and Wales and has a Bsc. (Hons) in Finance and Accounting.
Our Advisors
QuInAs Advisors
Prof Avirup Dasgupta
ADVISOR
Avirup Dasgupta
Avirup Dasgupta received his undergraduate, postgraduate and doctoral degrees from the Indian Institute of Technology (IIT) Kanpur. He then worked at the University of California Berkeley as a postdoctoral scholar and the project manager of the BSIM group and the Berkeley Device Modeling Center (BDMC). He is currently a faculty member at the Department of Electronics and Communication Engineering at the Indian Institute of Technology (IIT), Roorkee. He is an IEEE Senior Member and the winner of the IEEE EDS Early Career Award 2021. His work includes industry-standard compact model development and various aspects of semiconductor devices comprising physics, design and modelling.
Dr Wladek Grabinski
ADVISOR
Wladek Grabinski
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, in 1991. From 1991 to 1998, he was with IIS, ETHZ, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact model developments. Later, he was a Technical Staff Engineer with Motorola/Freescale Geneva Modeling Center. He is currently consulting for modeling, characterization, Verilog-A standardization, and parameter extraction of nanoscaled MOST for the design of RF CMOS ICs. He is an Editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design and also co-authored more than 70 papers. He is a member of ESSDERC TPC Track4: “Device and Circuit Compact Modeling” and the IEEE EDS Compact Modeling Technical Committee. He is involved in activities of the MOS-AK Association and has been serving as a Coordinating Manager since 1999.
Prof Pierre Fazan
ADVISOR
Pierre Fazan
Pierre Fazan was born in Lausanne, Switzerland where he obtained his Physics diploma and Ph.D. degrees at the Swiss Federal Institute of Technology (EPFL) in 1984 and 1988 respectively. From 1989 to 1997 he worked as process integration engineer then manager at Micron Technology, Boise USA, focusing on DRAM bit cell architecture and DRAM process integration. Among others, he pioneered the use of rough polysilicon for DRAM capacitors. In 1997 he was named Technology Manager at EM Microelectronics, Marin, Switzerland, and Professor at EPFL, Lausanne. In 2002 he founded Innovative Silicon Inc., to develop a new Floating Body RAM memory technology named Z-RAM. This company was funded by Venture Capitalists in 2004. Within Innovative Silicon, Pierre was the Chairman of the Board and acted first as the company CEO and then as CTO. This company was acquired by Micron Technology in 2010 and he joined Micron Technology as the IMEC assignee team on-site manager and as a Micron Fellow. He has authored or co-authored more than 100 papers and holds more than 200 US patents. Pierre served in program committees for the SOI, IEDM, VLSI, ISIF, ESSDERC, INFOS, ICMTD, IMW and ECS Conferences. In 2008 he was invited as a Technology Pioneer at the World Economic Forum (WEF) in Davos. Pierre is retiring from Micron Technology in May 2023.
Dr. J. Iwan Davies
ADVISOR
J. Iwan Davies
Dr. J. Iwan Davies obtained a B.Sc. in Chemistry from Imperial College, London and his Ph.D. on MOVPE Studies in Compound Semiconductors from the University of Manchester. He is a member of the Royal Society of Chemistry. With over 40 years-experience in the epitaxial growth by MOVPE of arsenide/phosphide III-V and selenide II-VI semiconductors, he has co-authored over 100 publications covering a very broad range of optoelectronic devices and material systems. Following a period of research and development at Plessey Research (Caswell) Ltd., he has managed the growth and characterization of epi-wafers, research & development, plant operations, product engineering, and chemical, safety & environmental systems during the last 35 years at IQE. He is currently IQE plc Group Technology Director, representing the company on numerous European associations, including Photonics 21 (Board of Stakeholders), European Photonics Industry Consortium, Aeneas and Important Projects of Common European Interest (IPCEI). He leads IQE plc in UK National and European Research Projects, supervises ~10 UK-based PhD studentships and has supported numerous EPSRC, NRN Wales, Centres for Doctoral Training and Knowledge Transfer Partnership projects with UK universities.
Contact Us
Address
QUINAS Technology
A035, Faraday Buildings
Physics Avenue, Bailrigg
Lancaster LA1 4YB
United Kingdom
A035, Faraday Buildings
Physics Avenue, Bailrigg
Lancaster LA1 4YB
United Kingdom
Phone
Registered Office
QUINAS Technology Limited
85 Great Portland Street, First Floor
LONDON W1W 7LT
United Kingdom
Registered in England and Wales.
Company Registration No. 14673840.
85 Great Portland Street, First Floor
LONDON W1W 7LT
United Kingdom
Registered in England and Wales.
Company Registration No. 14673840.
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Acknowledgements
ULTRARAM is developed in partnership with Lancaster University and funded by the EPSRC (under IAA grant EP/X525583/1 and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1), by the Materials Social Futures doctoral training Program of the Leverhulme Trust, by the European Commission via ATTRACT (grants 777222 and 101004462), by MSCA-ITN QUANTIMONY (grant 956548) and by the Innovate UK ICURe program.